One recent trend in circuit design has been to use high-level programming languages (HLLs) to design electronic circuits. For example, a circuit design can be specified initially as a program written in an HLL such as Fortran, C/C++, JAVA, or the like. This approach allows a developer to concentrate on an algorithmic solution to a problem rather than the specific hardware involved. A variety of different tools are available which effectively translate the HLL program into a synthesizable netlist or other software-based circuit representation. Tools for Compiling High Level Language into Massively Pipelined Systems (CHiMPS) provide means to compile programs written in languages such as C and Fortran into an intermediate language (“CHiMPS language”). The CHiMPS language specification can then be further processed to implement the design in a suitable combination of hardware (e.g., a field programmable gate array FPGA) and software.
Once the electronic circuit design is implemented in hardware, power consumption and performance (e.g., speed) are two factors that come into play, and often in a competing manner. Clock gating is one technique used to reduce power consumption. For example, tools can be used to analyze a hardware circuit to locate groups of flip-flops or latches that can be disabled under certain conditions. A control signal can then be generated based on those conditions to gate the clock signal to the identified flip-flops or latches. This can greatly reduce or eliminate the dynamic power consumption (switching power) of that portion of the circuit. In a typical design, clock gating can reduce total power by up to 30%.